RE: [sv-ec] Multiple triggering of assertions and clockings

From: Arturo Salz <Arturo.Salz_at_.....>
Date: Tue Feb 06 2007 - 15:02:04 PST
Jonathan,

Forbidding multiple clock triggers in the same time slot does not
disallow the methodology you suggest: untimed functional models that may
trigger additional activity in the DUT as part of the Reactive
processing. Multiple delta-cycles involving the Active/Reactive regions
is the way SystemVerilog is intended to work when Reactive processes
post events with no delay to which Active processes are sensitive. This
means that any signal, including a clock could be triggered from within
a Reactive process.

What we are trying to forbid is *the same* clock signal being triggered
more than once in the same time slot. Remember that unlike an un-timed
model (whether in Specman or not), clocking blocks and assertions both
sample their inputs in the Preponed (or previous Postponed) region,
hence, if their clocks were to trigger more than once in the same time
slot, the sampled values would not change. I imagine that this behavior
is not what users would expect, so it's best to flag the condition as an
error and alert users to this fact.

	Arturo

-----Original Message-----
From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of
Jonathan Bromley
Sent: Tuesday, February 06, 2007 12:45 PM
To: sv-ec@eda-stds.org
Subject: [sv-ec] Multiple triggering of assertions and clockings

After agreeing strongly that we should forbid multiple
triggerings of the clock of an assertion or a clocking
block within a given timestep, I find myself having 
second thoughts.

In Specman land, there is a commonly used approach
in which a verification environment can exercise
an untimed or even a null DUT in zero time.  This 
can be very useful when verifying untimed functional
models, and when checking-out the behavior of a
testbench without a live DUT present.  Each new 
round of activity in the verification environment
happens in the SAME timeslot. 

It's not exactly the same, but there is a reasonably
close analogy between Specman's behavior and the way
a testbench executes in Reactive - it executes
atomically with respect to the Active DUT, but can 
plant new events in the Active regions of the same
timeslot, starting a whole new round of activity at
the same moment of simulation time that, potentially,
can schedule further activity in the Reactive region
of the same timeslot.

If we outlaw multiple triggerings of assertion or
clocking in a given timeslot, this possibility is
out of reach because we demand that clock events
be separated in time - be in separate timeslots.

I'm not sure right now whether I think this is 
important, but it's certainly something I have not
heard discussed so far and it may be relevant for
people using SV to implement and verify untimed 
functional models.  At the very least, it provides
a motivation for allowing the use of #1step and
#Nstep as procedural delays - they could capture
the notion of "move to a new timeslot without 
worrying about how much you advance simulation time".
-- 
Jonathan Bromley, Consultant

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Received on Tue Feb 6 15:02:27 2007

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