RE: [sv-ec] cycle delays in assignments

From: Jonathan Bromley <jonathan.bromley_at_.....>
Date: Sat Feb 03 2007 - 01:16:17 PST
> I think the language will be most intuitive if ##n
> is always associated with the default clocking.

I completely agree, but if we do this it bars the way to
a VERY useful piece of functionality.

Dynamically instantiated verification objects can't have
access to the default clocking, since the latter is 
associated with a static scope.  Consequently, at present
I can't use ## at all in a class-based piece of code.
For the procedural ## delay I can easily get the 
functionality elsewise, but nonblocking intra-assignment
## is inaccessible [*] unless it inherits the target's 
clocking.  I think that's a pity.  

[*] I just thought: does this work?

  cb.tgt <= repeat (N) @(cb) expr;

If so, I have no problem with the loss of <=##.

Further note:  It's worth observing that EVERY
clocking drive in effect does this...

  cb.tgt <= ##0 expr;

where the ##0 is "line up with the current or next
cycle of cb".  Isn't that somewhat discontinuous
with <=## being associated with the default clocking?
--
Jonathan Bromley, Consultant

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Received on Sat Feb 3 01:17:16 2007

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