[sv-ec] SV: Attributes not allowed in constraint_block_item !!!

 Looking at the LRM, I noticed that attributes are not allowed in constraints. 
 This maybe a necessary feature if a vendor wants to add a particular attribute. 
 As I understand it, the IEEE chose not to standardize the algorithms behind SV's constrained 
 random generator and constraint solver. Therefore, it is both legal and "expected" for each tool to come up with
 different random values and constraint solutions. 
 
 We could add attributes as shown below: For example
 constraint XYZ
 {
 (* Vendor_ATTRIBUTE *) solve A before B;
 ...
 The current syntax for a constraint declaration is: 
 constraint_declaration ::=
 [ static ] constraint constraint_identifier constraint_block
 constraint_block ::= { { constraint_block_item } }
 constraint_block_item ::=
 solve identifier_list before identifier_list ;
 | constraint_expression 
   
 Should attributes be added to a constraint_block_item? ---------------------------------------------------------------------------
 Ben Cohen Trainer, Consultant, Publisher (831) 345-1759
 http://www.systemverilog.us/ ben_ f rom _systemverilog.us
 * Training for VMM, SVA and PSL
 * Co-Author: SystemVerilog Assertions Handbook, 2005 ISBN 0-9705394-7-9
 * Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
 * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
 * Component Design by Example ", 2001 isbn 0-9705394-0-1
 * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
 * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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