RE: [sv-ec] wait on event

Steve,

Agreed. This does mean that explicitly writing the Boolean expression
ought to be valid: wait( ev == null );

	Arturo

-----Original Message-----
From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of
Steven Sharp
Sent: Thursday, January 18, 2007 1:38 PM
To: sv-ec@eda.org; soumya@cal.interrasystems.com
Subject: Re: [sv-ec] wait on event

A wait statement waits for an expression to become "true".

In Verilog, a named event has no value, and cannot be used in an
expression other than an event expression (in an event control).

In SystemVerilog, a named event can be assigned to a named
event or compared to a named event or null.  I don't believe it
can be used in any other new contexts.  I don't believe that it
can be used in a condition and be implicitly treated as a
comparison to null.

So no, it is not legal to use a named event in a wait.  Anyone
trying to do so probably does not understand either named events
or waits.

Steven Sharp
sharp@cadence.com


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