A wait statement waits for an expression to become "true". In Verilog, a named event has no value, and cannot be used in an expression other than an event expression (in an event control). In SystemVerilog, a named event can be assigned to a named event or compared to a named event or null. I don't believe it can be used in any other new contexts. I don't believe that it can be used in a condition and be implicitly treated as a comparison to null. So no, it is not legal to use a named event in a wait. Anyone trying to do so probably does not understand either named events or waits. Steven Sharp sharp@cadence.com -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Thu Jan 18 13:41:21 2007
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