> module event_wait (input [7:0] in1,in2, output reg [7:0] out2); > event ev2; > > always @* > begin :B2 > out2 = in1 ~^ in2; > -> ev2; > wait (ev2); > end > endmodule I think it's clear enough; wait() expects a "boolean" expression. I imagine that your design intent is wait (ev2.triggered); Note, though, that in the example you give, that wait will proceed without time delay, since the triggered status of ev2 either is true already, or will become true during the current timeslot, thanks to the ->ev2 statement on the previous line. Alternatively you could of course do @(ev2); but I suspect it would not do what you want. Stupid question: is wait(ev2); a legal way to express "wait until the event handle ev2 is non-NULL" ? Not that civilized folk would ever do such a thing, of course... -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 Email: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Wed Jan 17 01:34:22 2007
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