[sv-ec] Mantis 1609: New updates?

  
 Mantis 1609 states  Quote: 
  It shall be illegal to have an import statement directly within a class scope. 
 
 1, What is the status of this mantis? Still under discussion? 
 2. If the import is outside the class and at root, then the only need for the import would be for synthesis of RTL since the import of a package would be seen by the RTL anyway from root. 
 3. Currently not all vendors have abided by current P1800 that allows the import within a class. 
 What about backward compatibility since current P1800 LRM allows import within a class? Users will need to make the necessary changes. 
 3. As of today there are several differences in tool support and understanding (or interpretation) of the LRM. Code that compiles and runs on one tool would most likely not execute on another tool, particularly when the advanced feature of the language are used. This import issue is only one of them.
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 Ben Cohen Trainer, Consultant, Publisher (831) 345-1759
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 * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
 * Component Design by Example ", 2001 isbn 0-9705394-0-1
 * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
 * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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