Hi, Kakoli - I believe it is legal but I can't think of a good reason to code this way. Do you have a reason to add a forever to an always_comb? always_comb is synthesizable but forever is not. BTW - your simple example has problems. The forever statement has no delay so you have a 0-delay loop that will make the simulator appear to be hung (it will run ... "forever!" without advancing simulation time) Regards - Cliff At 03:40 AM 10/23/2006, Kakoli Bhattacharya wrote: >Hello, > >Is forever statement illegal within an always_comb block? > >always_comb > forever out1 = in1*in2; > >Should the above eg give an error at compile time or at simulation? >Thanks, >Kakoli ---------------------------------------------------- Cliff Cummings - Sunburst Design, Inc. 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005 Phone: 503-641-8446 / FAX: 503-641-8486 cliffc@sunburst-design.com / www.sunburst-design.com Expert Verilog, SystemVerilog, Synthesis and Verification TrainingReceived on Mon Oct 23 07:38:04 2006
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