RE: [sv-ec] Mapping of ports between a testcase and testbench

According to 8.13, a port connection to an input or output port of a
module, interface, or program is an assignment-like context.

A port connection to an inout or ref port is not.

Also consider the test case in 

    http://www.eda-stds.org/sv-bc/hm/5047.html

-- Brad

-----Original Message-----
From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of
Kakoli Bhattacharya
Sent: Thursday, September 14, 2006 7:19 AM
To: sv-ec@eda.org
Subject: [sv-ec] Mapping of ports between a testcase and testbench

Hello,

Do we consider the mapping of the ports between a testcase and its
corresponding testbench an assignment-like context?

Thanks,
Kakoli