[sv-ec] Mapping of ports between a testcase and testbench

From: Kakoli Bhattacharya <kakoli_at_.....>
Date: Thu Sep 14 2006 - 07:18:32 PDT
Hello,

Do we consider the mapping of the ports between a testcase and its corresponding 
testbench an assignment-like context?

Thanks,
Kakoli
Received on Thu Sep 14 07:20:45 2006

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