Re: [sv-ec] use model for non-blocking event triggers

Since nobody else has responded, I'll take a stab:

I don't know that they were added for any particular use-model, or
for any interaction with SystemVerilog constructs.  They were added
for completeness and consistency within Verilog.  An event is like
a variable that has no data value, just the abstract concept of a
"value change".  Since variables can have their values changed with
blocking or nonblocking assignments, it also makes sense to be able
to create this abstract "value change" on an event using either
blocking or nonblocking semantics.  Otherwise, you might have the
bother of creating a 1-bit variable, initializing it, and toggling
it, because you wanted nonblocking semantics and there was no way
to do this with a named event.

One possible reason for this would be to avoid race conditions where
one process triggers the event before another starts waiting on it.
This is similar to the reason why the "triggered" property was added
to named events, but is a more Verilog-like solution.  It also provides
a finer degree of control than the "triggered" property.  Once the
"triggered" property is set, it stays set until simulation time
advances.  There is no way to use it to signal back and forth multiple
times in zero-delay.  The nonblocking event trigger could do so.

Steven Sharp
sharp@cadence.com