Re: [sv-ec] foreach iterates over unpacked arrays

According to P1800.10.5.3, "The number of [foreach] loop variables must
match the number of dimensions of the array variable. Empty loop
variables can be used to indicate no iteration over that dimension of
the array, and contiguous empty loop towards the end can be omitted.".

I'm not convinced there's a problem with this text.  But if there is,
it's that it's talking about the dimensions of the array variable,
instead of the dimensions of the array being iterated over.  Recall that
SystemVerilog does not have true multidimensional arrays, it has arrays
of arrays.  As it says in P1800.6.9.1.f, "The type of the slowest
varying dimension of a multidimensional array type is itself an array
type."

-- Brad