I looked through the LRM and do not find any statement that disallows a hierarchical reference to an object in a modport. In the example below I have a hierarchical reference being connected to a port of a module instance. The question is: Is it legal for me to make such connection? Specifically, is rtl rtl_1(.m (b_if.rtl_if.m), // LEGAL ??? In case you're wondering why this unusual style, it's because a top-level and testbench designer defined the interfaces, assuming that the RTL guy will use. But the RTL guy did not use the interface, and defined just straight ports. The question then becomes: Is the testbench correct? I believe that there misunderstanding in the community on this issue, and I would like some clarification. ------------------------ interface sysbus_if (input clk, input reset_n); timeunit 1ns; timeprecision 100ps; logic m; logic a; logic b; modport driver_if ( input m, output a, output b ); modport rtl_if ( output m, input a, input b ); endinterface : sysbus_if module rtl ( output logic m, input logic a, input logic b, input reset_n, input logic clk); endmodule : rtl module rtl_tb; // logic m; // logic a; // logic b; logic reset_n; logic clk; sysbus_if b_if(clk, reset_n); // IS THIS CORRECT ? rtl rtl_1(.m (b_if.rtl_if.m), .a (b_if.rtl_if.a), .b (b_if.rtl_if.b) ); // IS THIS CORRECT ALSO ? rtl rtl_2(.m (b_if.m), .a (b_if.a), .b (b_if.b) ); endmodule : rtl_tb ------------------------------------------------------------------------- - Ben Cohen Trainer, Consultant, Publisher (310) 721-4830 http://www.vhdlcohen.com/ ben_ f rom _abv-sva.org * Co-Author: SystemVerilog Assertions Handbook, 2005 ISBN 0-9705394-7-9 * Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0 * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8 * Component Design by Example ", 2001 isbn 0-9705394-0-1 * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1 * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115 ------------------------------------------------------------------------- --------Received on Fri Sep 9 17:07:06 2005
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