[sv-ec] Ambiguous Program Block Port Assignments??

Subject: Ambiguous Program Block Port Assignments??

Hi, All -

Next spec ambiguity?? - Program block ports

Attached is a small working example: porttest.v

=============

This example works with both ModelSim 6.1a and VCS version 2005.06

In default compile mode, the program block is making assignments to the 
program block ports (which also correspond to the device ports) using 
nonblocking assignments.

=============

If you use the compile switch +define+P1, the program block will make 
assignments to the same ports using blocking assignments. Since the 
declarations are part of the program block, could they be considered 
program block variables that can be assigned using blocking assignments (??)

This example works with ModelSim 6.1a but fails with VCS version 2005.06. 
VCS notes that a "Design variable can only be driven through and 
nonblocking assignment within a program." I'm not sure which implementation 
is "right" but I would like to make sure that all implementations recognize 
the same syntax. I would like to get this fixed real quick before 
implementations diverge on the standard.

=============

If you use the compile switch +define+P2, the program block will make 
assignments to an intermediate program variable that is then driven to the 
port through a continuous assignment. Of course, we cannot use nonblocking 
assignments with a continuous assignment so how should this work?

This example works with ModelSim 6.1a but fails with VCS version 2005.06. 
VCS again notes that a "Design variable can only be driven through and 
nonblocking assignment within a program." Are continuous assignments to 
program ports that drive design inputs illegal??

=============

Regards - Cliff


----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com
Expert Verilog, SystemVerilog, Synthesis and Verification Training