RE: [sv-ec] Program variables; Cycle delay (##) - email from michael.smith

Michael,

The way the LRM is currently written, I believe that program ports are
program variables except in the case of ref ports. Input and output
ports are conceptually continuous assignments between variables on one
side to variables on the other side. Inouts can only be wire kinds and
you can't procedurally assign to wires in any case.

That said, it is also my opinion that the rules requiring NBAs to
non-program variables and blocking assignments to program variables from
within a program block should be removed and left as a rule for a lint
checker. There are too many loop holes that get around the scheduling
restrictions. For example, a program can call a function in a module to
do a blocking write to a module variable. And by not allowing NBAs to
program variables, you can just as easily produce races between
different components in the testbench.

The assignment statement that the user writes to a clocking block output
is an indirect assignment, not really an NBA. Anytime you make an
assignment to a clocking block variable, the clocking block definition
controls the semantics of the actual assignment to the underlying
variable, regardless of whether that variable is program or design
variable. The BNF calls this a clocking_drive, not an assignment
statement.

Dave

> -----Original Message-----
> From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of
Neil
> Korpusik
> Sent: Wednesday, July 13, 2005 5:32 PM
> To: SV_EC List
> Subject: [sv-ec] Program variables; Cycle delay (##) - email from
> michael.smith
> 
> Forwarding email that bounced from the reflector.
> 
> 
> -------- Original Message --------
> Subject: BOUNCE sv-ec@eda.org:    Non-member submission from ["Michael
> Smith" <michael.smith@doulos.com>]
> Date: Wed, 13 Jul 2005 00:59:40 -0700 (PDT)
> Subject: Program variables; Cycle delay (##)
> From: "Michael Smith" <michael.smith@doulos.com>
> 
> 
> Program Variables
> -----------------
> Are the ports of a program considered to be "program variables"?
> I would have thought "yes", but it depends what "in the scope of a
> program" means.
> 
> So, am I correct in saying that a program's outputs should be
> assigned using blocking assignments?
> 
> 	program (output logic v);
> 	  initial v = 1;
> 	endprogram
> 
> Is this the intent?
> 
> Cycle delay (##)
> ----------------
> 
> Given,
> 
> 	clocking cb @(posedge clk);
> 	  output o;
> 	endclocking
> 
> 	initial begin
> 	      cb.o <= 0;
> 	  ##1 cb.o <= 1;
> 	end
> 
> what happens?
> 
> Thanks,
> 
> Mike Smith
> --
> Michael Smith
> Senior Consultant
> 
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> ---------------------------------------------------------------------
> Neil Korpusik                                     Tel: 408-720-4852
> Staff Engineer                                    Fax: 408-720-4850
> Frontend Technologies - ASICs & Processors (FTAP)
> Sun Microsystems
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