[sv-ec] Program variables; Cycle delay (##) - email from michael.smith

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-------- Original Message --------
Subject: BOUNCE sv-ec@eda.org:    Non-member submission from ["Michael Smith" <michael.smith@doulos.com>]
Date: Wed, 13 Jul 2005 00:59:40 -0700 (PDT)
Subject: Program variables; Cycle delay (##)
From: "Michael Smith" <michael.smith@doulos.com>


Program Variables
-----------------
Are the ports of a program considered to be "program variables"?
I would have thought "yes", but it depends what "in the scope of a
program" means.

So, am I correct in saying that a program's outputs should be
assigned using blocking assignments?

	program (output logic v);
	  initial v = 1;
	endprogram

Is this the intent?

Cycle delay (##)
----------------

Given,

	clocking cb @(posedge clk);
	  output o;
	endclocking

	initial begin
	      cb.o <= 0;
	  ##1 cb.o <= 1;
	end

what happens?

Thanks,

Mike Smith
--
Michael Smith
Senior Consultant

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