[sv-ec] How do I record coverage information of Fibonacci series, using covergroup

From: Tapan Kapoor <tkapoor_at_.....>
Date: Fri Jul 01 2005 - 01:05:02 PDT
Hi,
 
The question is about System Verilog covergroup usage. How to record
coverage information of any design signal which has a non-continuous
spectrum like Fibonacci series? The range of Fibonacci series is
configurable through parameters i.e. two parameter MIN_VAL and MAX_VAL.
These parameters provide bounds for the value-distribution of the
signal, which means the range would differ from application to
application. If I use whole range in the bin definition, as shown in the
code fragment below:
-----------------------------------------------
integer fib_signal;
always @ (input_data)
        fib_signal = input_data;
 
covergroup fibonacci_cover @ (posedge clock)
        rec: coverpoint fib_signal
        {
            bins data[] = {[MIN_VAL:MAX_VAL]};
        }
endgroup
------------------------------------------------
the numbers which are not in the fibonacci series appear as holes, since
they are never likely to appear. Alternatively, if there were a
construct to define bin-range through a function as below:
----------------------
    bins data[] = fibonacci_function(MIN_VAL, MAX_VAL)
----------------------
where the function "fibonacci_function" is repetitively invoked to get
all the fibonacci values within the range, it would help defining the
range accurately. 
 
Please suggest if there is a way to code the above-described
functionality within the existing language. OR is it possible to include
the above sort of construct in the covergroup. It would be useful for
many other application where the input data-stream is non-continuous
spectrum like recording even-parity, odd-parity, one-hot etc.
 
 
Thanks & regards,
 
Sandeep / Tapan. 
 
 

"You must be the change you want to see in the world" : Mahatma Gandhi 
  

 



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Received on Fri Jul 1 01:05:21 2005

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