Re: [Fwd: [sv-ec] Type casting issue]

>byte r2;
>bit [2:0] r1;
>
>assign r1 = 3'b111;
>assign r2 = byte'(r1);

I don't know what the official SV answer is on this. However, I got the
impression that a type cast was supposed to work the same way as an
assignment to a variable of that type. If r1 were being assigned to a
signed 8-bit object in Verilog-2001, it would be zero-extended. The
signedness of the LHS of an assignment does not affect the signedness
of the RHS.

Steven Sharp
sharp@cadence.com
Received on Fri Aug 13 13:27:12 2004