[Fwd: [sv-ec] Type casting issue]

  Hi,
Can anyone please reply this one.
Thanks
Kausik

-------- Original Message --------
Subject: [sv-ec] Type casting issue
Date: Mon, 31 May 2004 19:17:07 +0530
From: Kausik Datta <kausikd@cal.interrasystems.com>
Reply-To: kausikd@cal.interrasystems.com
Organization: Interra Systems India Pvt. Ltd.
To: sv-ec@eda.org, sv-ac@eda.org

Hi,
For the following design, what is the expected output
If we do the sign extension of r1 ( as byte is signed), the output becomes

r2 = 11111111

But if we do unsigned padding of r1 ( as it is unsigned ) the output
comes as

r2 = 00000111.

Please let me know what should be done for such type-casting.(LRM is not
clear)

Design
------
module test;

byte r2;
bit [2:0] r1;

assign r1 = 3'b111;
assign r2 = byte'(r1);

initial
begin
#1 $display("r2 = %b", r2);
end

endmodule

Thanks
Kausik
Received on Thu Aug 12 04:12:38 2004