>> Specifically about module overloading, Verilog has the 'configuration'
>> mechanism, which is maybe what Brad was trying to refer to. (Brad mentioned
>> SV 3.1a 23.2, but maybe he meant 22.2). However, neither the configuration
>> mechanism nor generates, nor even their combination seems to allow to you to
>> choose a different version of the SAME module depending on parameter values.
>>
>> Shalom
>
>I'm not familiar with the configuration mechanism - but I'd be glad to
>hear how it could be used to solve the problem:
As Shalom said, I don't think configurations help with this. I think they
would let you bind a module based on where it appears in the hierarchy, but
not based on its parameter values.
Generates are the Verilog mechanism for changing what gets instantiated in
the design based on parameter values.
>The problem is how do we select the right transistor model depending on
>instance parameters (length, width, fingers etc.), and we would like to be
>able to add more special cases at any time without rewriting much code.
Without knowing more about what these models look like, it is hard to
provide feedback about how generates or ordinary parameterization could
be used. However, generates allow instantiating completely different
modules based on parameter values, so they are certainly powerful enough.
Steven Sharp
sharp@cadence.com
Received on Tue Jun 22 16:29:35 2004
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