[sv-ec] Quick poll for AMS extension to overload modules

There is a proposal in the latest draft AMS LRM for "paramsets" (sec. 7.3):

http://www.eda.org/verilog-ams/htmlpages/public-docs/AMS-LRM-2-2-draft-e.pdf

What this does is allow different modules to be selected for a given
instance depending on the instance parameters, i.e. the paramset name is
treated as being like a module name, and there are multiple paramsets
with the same name - one is selected according to the instance
parameters and its associated module wil be instantiated. There is
nothing about this functionality that restricts it to analog usage.

In my opinion this is just a very specific case of module overloading,
and it might be better to use a more general syntax which would allow
extension into module overloading based on port types.

So my question is: would you prefer to have paramsets for module
overloading or a more general extension of the [macro]module syntax to
perform the task?

Bear in mind: Verilog-AMS will be merged with SV at some point in the
future, so if the SV-EC decides to add module overloading by a
different mechanism we could end up with multiple mechanisms that might
not be reconcilable.

Kev.
Received on Tue Jun 15 12:50:04 2004