Subject: [sv-ec] FW: statement ##5; not in grammar and PROPOSAL (BNF)
From: Brad Pierce (Brad.Pierce@synopsys.com)
Date: Thu Dec 18 2003 - 18:37:49 PST
I am forwarding a clocking domain erratum that was
reported to the SV-BC by Hermann Ilmberger.
The issue is that cycle_delay was never added to
procedural_timing_control. Also, Syntax 15-2
excerpts the wrong nonterminals from Annex A.
Attached is a BNF proposal.
-- Brad
-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org]On Behalf Of
Hermann.Ilmberger@infineon.com
Sent: Wednesday, December 17, 2003 8:52 AM
To: sv-bc@eda.org
Subject: [sv-bc] statement ##5; not in grammar
Chapter 15 of the LRM has several examples with cycle_delays like
## 5; // wait 5 cycles (clocking events) using the default clocking
Chapter 15.10 talks about a "cycle delay statement".
How can the statement above be produced from the formal grammar?
Here is what I can find, none allows the simple ##5; statement:
A.6.11 Clocking domain
cycle_delay ::=
## expression
clocking_drive ::=
clockvar_expression <= [ cycle_delay ] expression
| cycle_delay clockvar_expression <= expression
A.2.10 Assertion declarations
cycle_delay_range ::=
## constant_expression
| ## [ cycle_delay_const_range_expression ]
sequence_expr ::=
cycle_delay_range sequence_expr { cycle_delay_range sequence_expr }
| sequence_expr cycle_delay_range sequence_expr { cycle_delay_range
sequence_expr }
| ...
-Hermann
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