[sv-ec] Erratum in Syntax 10-2

Subject: [sv-ec] Erratum in Syntax 10-2
From: Brad Pierce (Brad.Pierce@synopsys.com)
Date: Thu Dec 18 2003 - 14:37:18 PST

• Next message: Brad Pierce: "[sv-ec] FW: statement ##5; not in grammar and PROPOSAL (BNF)"
• Previous message: Brad Pierce: "Re: [sv-ec] Re: SystemVerilog 3.1a LRM"
• Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

Syntax 10-2, function_data_type, was not updated
to reflect the changes in Annex A.

I'm the culprit, because my proposal

     http://www.eda.org/sv-ec/hm/att-1465/01-ERR-9_revised.htm

neglected to mention Syntax 10-2.

-- Brad

• Next message: Brad Pierce: "[sv-ec] FW: statement ##5; not in grammar and PROPOSAL (BNF)"
• Previous message: Brad Pierce: "Re: [sv-ec] Re: SystemVerilog 3.1a LRM"
• Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

This archive was generated by hypermail 2b28 : Thu Dec 18 2003 - 14:40:49 PST