Subject: [sv-ec] FW: BNF vs LRM section issue (from Kausik Datta at interrasystems.com)
From: David W. Smith (David.Smith@synopsys.com)
Date: Sun Nov 16 2003 - 10:30:22 PST
Email forward.
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Subject: BOUNCE sv-ec@eda.org: Non-member submission from [Kausik Datta
<kausikd@cal.interrasystems.com>]
> >From owner-sv-ec Fri Nov 14 00:23:55 2003
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> From: Kausik Datta <kausikd@cal.interrasystems.com>
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> Organization: Interra Systems India Pvt. Ltd.
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> Subject: BNF vs LRM section issue
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> Hi,
> can anyone comment on this?
>
> There is a section in the LRM(10.2) which says that a specific formal
> argument of a static task can be declared as automatic and vice versa :
> "System Verilog extends this capability by allowing specific formal
> arguments and local variables to be declared as automatic within a
> static task, or by declaring specific formal argument and local
> variables as static within an automatic task."
>
> But according to BNF, formal argument can not be declared as
> static/automatic.
>
> Thanks
> Kausik
>
>
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