Subject: [sv-ec] comments on the LRM changes
From: Francoise Martinolle (fm@cadence.com)
Date: Mon Mar 24 2003 - 09:36:29 PST
Comments on LRM changes: mostly editorials
12.6.3
typo: exam-ple (first paragraph after the verilog code example)
12.7.1 wait_order()
"The wait_order construct suspends the calling process until all the specified events are triggered in the given order (left to right), *or any * of the un-triggered events is triggered out of order and causes the operation to fail."
The above sentence needs to be rewritten more clearly as 2 sentences.
The wait_order construct suspends the calling process until all the specified events are triggered in the given order (left to right), *or any * of the un-triggered events is triggered out of order. The wiat_order task will fail
is any of the untriggered events in the list is triggered out of the specified order.
12.8.1: typo "For example:"
12.8.2:
Did we really vote to make this undefined? I think users will complain about
vendor implementation differences if we leave this undefined. They will
use the null assignment to cause the event variables to be reclaimed but
then they will have runtime errors or different behaviour of their
code which uses these events unless they enclosed them with a named block
and disable that block.
event E1 = null;
@ E1; // undefined: may block forever or not at all
wait( E1.triggered ); // undefined
section 13.2
typo: "The signal_identfier"
section 5.4:
typo "run-time expressions"
section 15.1
typo: "synchronized, "
section 15.2:
typo "SystemVerilog "
section 15.2:
the title of the bnf for program blocks is wrong.
"Syntax 15-1—Module declaration syntax (excerpt from Annex A)"
In the program example the comment below shoud say that p1 and p2 are instantiated once iff the module test which contains them is instantiated once only. Becuase if module test is instantiated multipl times in the hierarchy
so are the programs p1 and p1.
// p1 and p2 are implicitly instantiated once
section 15.3:
typo "independent"
section 15.4
typo : out-puts
section 15.5:
If the same task is called from within a program then the statement S1 will execute when the Reactive region is processed,
after variable b may been updated by nonblocking assignments. Statement S2 always executes when the first Active region is processed.
I would modify above paragraph as:
after variable b may *have* been updated by nonblocking assignments made by thedesign calling the task.
Is the second sentence correct? I understood that NBA inside a task called
from a program would execute in the next NBA region.
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