Subject: RE: [sv-ec] Alternate Class Proposal Version 1.1
From: Jay Lawrence (lawrence@cadence.com)
Date: Fri Mar 14 2003 - 07:22:20 PST
In the spirit of trying to get through all the agenda items today, I've
attached a BRIEF (a little over 1 page) rebuttal to Arturo's analysis.
It looks at the requirements he extracted and conclusions he came to
with comments.
The ONLY thing being proposed is a syntactic change at this time to
allow for FUTURE extensions.
Attempts to characterize this proposal as one on static classes or
addition of pointers to SystemVerilog are unwarranted, it does neither.
Such extensions would need to be carefully designed to preserve the
safeness of pointers and performance. The proposal was not intended as a
design of these constructs; the examples were give simply to demonstrate
the kinds of difficulties that would occur in the future.
Jay
===================================
Jay Lawrence
Architect - Functional Verification
Cadence Design Systems, Inc.
(978) 262-6294
lawrence@cadence.com
===================================
> -----Original Message-----
> From: Arturo Salz [mailto:Arturo.Salz@synopsys.com]
> Sent: Friday, March 14, 2003 7:38 AM
> To: sv-ec@eda.org
> Subject: Re: [sv-ec] Alternate Class Proposal Version 1.1
>
>
> Attached is an analysis and critique of the alternate class proposal.
>
> Contrary to Jay's comments, the alternate proposal does create
> explicit and arbitrary unsafe pointers. This, I'm sure, was not an
> attempt to mislead but an honest oversight.
>
> Arturo
>
>
>
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