Subject: Re: $sv-ec Re: SV_EC September4,02 testbench discussion presentation
From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Fri Sep 06 2002 - 12:09:47 PDT
Hi, All -
Francoise has asked some good questions and Alec has shared his opinion
(see Alec's email). Let me share my differing opinion.
At 06:38 PM 9/5/02 -0400, Francoise Martinolle wrote:
>Thanks to Medhi for doing the presentation and not only proactively
>looking at the conflicts between SV and VERA but also proposing
>resolutions. The presentation
>helped me to understand the differences between SV and VERA and the
>testing features that VERA supports. I think that VERA has some valuable
>concepts; in particular I like the semaphores and mailboxes (even though I
>would prefer to see them implemented as classes).
>
>After the meeting as I was flying back to Boston, I spent some time
>thinking about how would VERA fit in systemVerilog. In order to do that I
>felt that I needed to step back and think about the objectives and use of
>a testbench language in order to evaluate if VERA would be a suitable donation.
>
>First I would like to raise some questions around the language
>requirements for systemVerilog. I apologize if this was discussed before
>as I am not aware of it and I could not find anything on it in the email
>threads on this working group. Please point me to a requirement document
>if one exists, otherwise can someone try to answer my questions?
>These answers will guide me to picture and judge how we can design a
>language which can be adequate for testing and hardware design.
>
>1. Is it necessary for a hardware description language which is used for
>design to contain language constructs for testing?
> Should SV contain everything for testing purpose, or should SV only
> contain provision to
> integrate easily with a testbench program?
Not necessary but very desirable.
>2. would the engineer who uses SV for designing his system also be the
>same engineer who writes the tests?
All too frequently the answer is yes. In almost all small companies and in
many large companies the designer also does the verification. In some of
these companies, two designers will test each others design to get a second
set of eyes to look at the problem. We could debate that all companies
should have separate verification teams for very good reasons, but
sometimes economics play a larger role.
>3. Should'nt a testbench language be HDL independent?
>
>note: VERA has many language independent features (classes, lists, process
>threads...) modifying VERA syntax and semantics to fit within SV may
>conflict with that requirement.
No. Many designers still use Verilog for verification because they can't
afford a second suite of tools. This has always been one of the advantages
to choosing and HDL such as Verilog. The same language can be used for
design (RTL or behavioral) and test.
>4. Shouldn't the testbench program/module be completely separated from the
>HDL design?
> If not, what are the advantages of embedding the tests in the design?
> I see the disadvantage that it would require the design to be
> recompiled every time I
> want to use a new test program.
No.
Advantages. easy and seamless probing between the languages. I only have to
learn one language (even though there will now be more to learn to take
advantage of the verification component).
Incremental compile fixes the recompile issue or other techniques of
reading stimulus from a file already called from the verification
environment avoids the problem altogether. On the other hand, transferring
stimulus across a PLI boundary is often much more costly than a recompile.
>5. What are the various kinds/types/scenarios of tests that one may want
>to do and that the language should support? Do they have different scope?
Some of the better test environments involve a virtual-system wrapper
around the design. I like everything I see in the new Vera donation and
will still want more in the future. The ability to use the high-level
constructs for both
>6. VHDL and Verilog and also PLI have been used for writing testbenches,
>what were their weaknesses and strengths in their testing capabilities?
> Is SV or VERA addressing these?
Strength - part of the same language. Although there are superior options
(Vera, Versiity) to building better test environments, Verilog could still
be used if budget did not permit acquisition of the better tools.
Weakness - required too much coding to do high-level verification
environments. SV addresses this in many ways. Implicit port connections
make instantiation of a large model into a testbench a breeze. Interfaces
accomplish similar goals. Record data types facilitate packet-like testing.
Queues or mail boxes facilitate variable length pipeline testing. I am sure
there is much more.
>There may be more questions but these are the first ones which came up to me.
>I would really appreciate if some people could share their opinions and
>provide
>some answers to my questions.
David has appropriately pointed out that Vera and similar donations fall
well within the SV mission statement. As a user who often has to use
Verilog to build my verification environment, I welcome enhancements that
make that job easier.
I proposed in our meeting on September 4th that the EC should accept the
revised Synopsys Vera donation. That proposal was postponed until the Sept
16 SV-EC meeting and I am looking forward to accepting the donation at that
time. After accepting the donation, we can get down to the nitty gritty of
debating exact syntax. I am very pleased with the work the Synopsys folks
did to align the Vera donation to the SV syntax. Kudos to the Synopsys team
that made the presentation.
I know it is going to be tough for vendors to add support for the new
syntax to their tools but as a user, I am looking forward to those additions.
>Francoise
> '
Regards - Cliff
----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com
Expert Verilog, Synthesis and Verification Training
This archive was generated by hypermail 2b28 : Fri Sep 06 2002 - 12:13:33 PDT