Subject: $sv-ec Re: SV_EC September4,02 testbench discussion presentation
From: Wolfgang.Ecker@Infineon.Com
Date: Mon Sep 09 2002 - 01:23:28 PDT
Hi,
a single HDVL environment for verification and design has several
proven benefits:
* Clear semantic definition at the interfaces
* Less learning effort and more flexibility in associating development
tasks
* Less tools, which means less tool learning effort and less tool
interaction (we just passed a 9 month nighmare in clarifying a
bug, which occured between a HDL simulator and a HVL environment)
What I expect from the direct C-Interface is an easy to use and fast
intergration of functional descriptions. I see this as a good extension
of the PLI.
The Drawbacks is that the HDVL becomes quite complex, i.e. Verilog
looses its benefit of beeing a simple language (or as said beeing
simpler than VHDL). Specific views or subsets of vendors may hinder
compatibility.
The risc of SystemVerilog extension towards HDVL is that it might
become a heterogenious language.
Best regards,
Wolfgang
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