[sv-bc] Re: [sv-ac] Restrictions over hierarchical reference of checker variable

>
> In SV 2009 draft 7a LRM, it is mentioned that (section 17.7.1 Checker
> variable assignments) It shall be illegal to reference a checker variable
> using its
> hierarchical name in assignments
>
> So is it allowed to refer hierarchical name of checker variable anywhere
> else (e.g. if condition etc), or hierarchical reference is completely
> disallowed for checker variable?

[Ben] It would be illegal to refer hierarchical names of a checker
In fact the LRM 17.7.1 shows this example:
module m(...)
...
check my_check(...);
...
*wire x = my_check.a; // Illegal*
bit y;
...
always @(posedge clk) begin
*my_check.a = y; // Illegal*
...
end
...
endmodule


> Is the following example legal?
>
> checker check(...)
> bit a;
> ...
> endchecker
> module m(...)
> ...
> check my_check(...);
> always @(posedge clk) begin
> if (my_check.a) // Is it allowed?
> begin end
> end
> endmodule
>
> If it is legal, then a follow-up question will come up - is it allowed
> to use hierarchical reference of checker variable in any part of RHS (as
> select expression of another expression or as normal expression) of
> procedural assignment? For e.g.
>
> checker check(...)
> bit a;
> ...
> endchecker
> module m(...)
> ...
> check my_check(...);
> bit y;
> int z;
> ...
> always @(posedge clk) begin
> y = my_check.a; // Is it allowed?
> y = z[my_check.a]; // Is it allowed?
> end
> endmodule
>
> I could not get the answer from the LRM.
>
> --
> Regards
> Surya
>
>
>
>
>
> --
> This message has been scanned for viruses and
> dangerous content by MailScanner, and is
> believed to be clean.
>
>

-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.