[sv-bc] Restrictions over hierarchical reference of checker variable

Hi,
In SV 2009 draft 7a LRM, it is mentioned that (section 17.7.1 Checker
variable assignments)
— It shall be illegal to reference a checker variable using its
hierarchical name in assignments

So is it allowed to refer hierarchical name of checker variable anywhere
else (e.g. if condition etc), or hierarchical reference is completely
disallowed for checker variable?
Is the following example legal?

checker check(...)
bit a;
...
endchecker
module m(...)
...
check my_check(...);
always @(posedge clk) begin
if (my_check.a) // Is it allowed?
begin end
end
endmodule

If it is legal, then a follow-up question will come up - is it allowed
to use hierarchical reference of checker variable in any part of RHS (as
select expression of another expression or as normal expression) of
procedural assignment? For e.g.

checker check(...)
bit a;
...
endchecker
module m(...)
...
check my_check(...);
bit y;
int z;
...
always @(posedge clk) begin
y = my_check.a; // Is it allowed?
y = z[my_check.a]; // Is it allowed?
end
endmodule

I could not get the answer from the LRM.

-- 
Regards
Surya





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