[sv-bc] Cycle delay in class

In LRM there is definition:
"A default clocking is valid only within the scope containing the default
clocking specification. This scope includes the module, interface, or
program that contains the declaration as well as any nested modules or
interfaces. It does not include instantiated modules or interfaces."
 
IMO default clock should also be valid in nested class - se the definition
should be changed:
"A default clocking is valid only within the scope containing the default
clocking specification. This scope includes the module, interface, or
program that contains the declaration as well as any nested modules or
interfaces or classes. It does not include instantiated modules or
interfaces."

 

 

DANiel

 


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