Hi Shalom/Steven,
encryption_envelope as:
encryption_envelope::=
{ encrypt_specification }
protect_begin_directive
source_text
protect_end_directive
Regards Surya
Dhiraj, The capability was not overlooked, as it existed in the Verilog standard well before adoption by VHDL. The text describing protection envelopes is different between the 1076-2008 and 1364-2005/1800-2005. The ordering of directives must be inferred from the Verilog text due to the larger set of supported use cases. While the text is different, then intended language structures should be compatible (if you are implementing components intended for both languages). Shalom correctly identifies the clauses you must refer to in the P1800 draft. Note that the principal difference will be the prefix of the directives. In SystemVerilog you will begin them with "`pragma protect" where VHDL uses "`protect". VHDL also trims the list of pragma keywords to force a particular use model and uses the BNF description to limit the textual structures you are allowed to create. If you have questions regarding encryption, the P1735 working group is a good forum to address this technology, and how it is handled across the language boundaries. P1735 recommends changes to the language working groups to help DASC keep those standards in sync. Some of those changes are present in this ballot round, and as more issues get resolved, we will continue to recommend changes to keep the relevant standards aligned and moving forward. For more info on P1735 see: http://www.eda.org/twiki/bin/view.cgi/P1735/WebHome /sjd Bresticker, Shalom wrote:It is organized a little differently in System/Verilog. The protect directive exists as "`pragma protect". The description is the BNF from the `pragma compiler directive in 22.11, and examples and textual descriptions and tables in Clause 34. Shalom ------------------------------------------------------------------------ *From:* Surya Pratik Saha [mailto:spsaha@cal.interrasystems.com] *Sent:* Tuesday, September 15, 2009 5:37 PM *To:* Bresticker, Shalom *Cc:* Dhiraj Kumar Prasad; sv-bc@server.eda.org *Subject:* Re: [sv-bc] Query related protect dirctive which is present in VHDL-2008 but not in verilog/System verilog. Hi Shalom, Nope, I did not see that type of rule in either Verilog 2005 LRM or System Verilog LRM. Can you please specify any particular sub-section mentioning that similar rule as I mentioned in my last mail. Regards Surya -------- Original Message -------- Subject: Re:[sv-bc] Query related protect dirctive which is present in VHDL-2008 but not in verilog/System verilog. From: Bresticker, Shalom <shalom.bresticker@intel.com> To: Surya Pratik Saha <spsaha@cal.interrasystems.com> Cc: Dhiraj Kumar Prasad <dhiraj@cal.interrasystems.com>, "sv-bc@server.eda.org" <sv-bc@eda.org> Date: Tuesday, September 15, 2009 7:57:51 PMI was referring to the SV-2009 LRM. The corresponding sections in the Verilog-2005 LRM are 19.10, 28.3 and 28.4. Shalom ------------------------------------------------------------------------ *From:* Surya Pratik Saha [mailto:spsaha@cal.interrasystems.com] *Sent:* Tuesday, September 15, 2009 5:25 PM *To:* Bresticker, Shalom *Cc:* Dhiraj Kumar Prasad; sv-bc@server.eda.org *Subject:* Re: [sv-bc] Query related protect dirctive which is present in VHDL-2008 but not in verilog/System verilog. Hi Shalom, To be specific, in VHDL 2008 LRM, there is a BNF for encryption_envelope as: encryption_envelope::= { encrypt_specification } protect_begin_directive source_text protect_end_directive This type of rule is missing in any version of Verilog/System Verilog LRM. Also I could not match this with the section number you mentioned. Please let us know your comments on that. Regards Surya -------- Original Message -------- Subject: Re:[sv-bc] Query related protect dirctive which is present in VHDL-2008 but not in verilog/System verilog. From: Bresticker, Shalom <shalom.bresticker@intel.com> To: Dhiraj Kumar Prasad <dhiraj@cal.interrasystems.com> Cc: "sv-bc@server.eda.org" <sv-bc@eda.org>, Surya Pratik Saha <spsaha@cal.interrasystems.com> Date: Tuesday, September 15, 2009 7:05:39 PMSee section 22.11 for pragma directives in general and sections 34.4 and 34.5 for protect pragmas in particular. Shalom ------------------------------------------------------------------------ *From:* Dhiraj Kumar Prasad [mailto:dhiraj@cal.interrasystems.com] *Sent:* Tuesday, September 15, 2009 4:18 PM *To:* Bresticker, Shalom *Cc:* sv-bc@server.eda.org; Surya Pratik Saha *Subject:* Re: [sv-bc] Query related protect dirctive which is present in VHDL-2008 but not in verilog/System verilog. Hi Shalom, Might my query was not clear. What I want to know is this that in VHDL-2008, protect directive has encryption envelope and decryption envelop and those envelope has BNF mention there. i.e what are the different thing that an encryption or decryption envelope can have but SV-2009 don't have that kind of BNF. So my query is this that was it overlooked??. Regards, dhiRAj Bresticker, Shalom wrote:This is described in Clause 34 Protected envelopes. Shalom-----Original Message----- From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org] On Behalf Of Dhiraj Kumar Prasad Sent: Tuesday, September 15, 2009 3:49 PM To: sv-bc@server.eda.org Cc: Dhiraj Kumar Prasad; Surya Pratik Saha Subject: [sv-bc] Query related protect dirctive which is present in VHDL-2008 but not in verilog/System verilog. Hi, I have a query related protect directive. In VHDL-2008,there is a directive named "protect directive" which is used for encryption/decryption of the source text. In SV-2009,there is nothing like protect directive of VHDL-2008. So my query is this that whether it is not necessary in Verilog/System verilog or it was overlooked??. Regards, dhiRAj--------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. 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