[sv-bc] Referencing non LRM constructs such as `uselib in LRM

Hi,
`uselib is a non LRM construct, though most of the standard simulators 
and tools support it as Verilog-XL does. Is there any chance to make it 
standardized and integrated in SV LRM.

Also, I saw in LRM section "23.11 Binding auxiliary code to scopes or 
instances"  there is a reference of `uselib. If there is no plan  to 
make `uselib standardized then a non-LRM construct should not be 
referred in LRM.

-- 
Regards
Surya




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