[sv-bc] Is ordering defined while connecting formals/actuals for a function?

Hi, 

 

Please consider following testcase:- 

 

module reduced(in1,next_instr);

input logic [9:0]   in1;

output logic[11:0]next_instr;

reg [9:0]   prg_cnt;

reg [1:0]   gp_pc;

reg        gp;

 

always @*

begin

  prg_cnt=0;

  gp_pc=0;

  gp=0;

  next_instr = next_instr_addr((prg_cnt = (gp_pc = (gp = 1))),gp_pc,gp);

end

 

function [11:0] next_instr_addr;

input logic [9:0]   prg_cnt;

input  logic[1:0]   gp_pc;

input  logic        gp;

   begin

      next_instr_addr = prg_cnt + gp_pc + gp;

   end

endfunction

 

endmodule

 

 

This query is especially about the statements highlighted in blue. I am
curious as to how it should be evaluated & what the expected output is.
I would appreciate if I am pointed to relevant section in LRM that deals
with this. I could not find anything about the order in which function
formals/actuals should be connected. 

 

Thanks & regards,

-Gauraw

 


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