[sv-bc] Query on defparam

Hi,
The following section in the "IEEE Standard for System Verilog—Unified 
Hardware Design, Specification,and Verification Language" (IEEE Std 
1800), section 20.2,page no.351: mentions

"Verilog does not permit a defparam statement within an array of 
instances to modify a parameter outside the hierarchy of the instance 
defining the defparam (see 12.2.1 of IEEE Std 1364)"

12.2.1 of IEEE Std 1364 says :


"Using the defparam statement, parameter values can be changed in any 
module instance throughout the design using the hierarchical name of the 
parameter. See 12.5 for hierarchical names.

However, a defparam statement in a hierarchy in or under a generate 
block instance (see 12.4) or an array of instances (see 7.1 and 12.1.2) 
shall not change a parameter value outside that hierarchy.

Each instantiation of a generate block is considered to be a separate 
hierarchy scope. Therefore, this rule implies that a defparam statement 
in a generate block may not target a parameter in another instantiation 
of the same generate block, even when the other instantiation is created 
by the same loop generate construct.

For example, the following code is not allowed:
genvar i;
generate
for (i = 0; i < 8; i = i + 1) begin : somename
flop my_flop(in[i], in1[i], out1[i]);
defparam somename[i+1].my_flop.xyz = i ;
end
endgenerate

Similarly, a defparam statement in one instance of an array of instances 
may not target a parameter in another instance of the array."

The text is clear with respect to a generate block but how a defparam 
can be specified inside an array of instance is not clear. Can you 
please give some e.g. for my understanding.

-- 
Regards
Surya




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