RE: [sv-bc] Confusion about case statement

I think the reason is that you have declared p and out1 as type bit, which is 2-state.
So p becomes 2'b10 instead of 2'b1x.
 
Shalom


________________________________

	From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org] On Behalf Of Surya Pratik Saha
	Sent: Thursday, October 16, 2008 3:20 PM
	To: sv-bc@server.eda.org
	Cc: 'Pradip Mukhopadhyay'
	Subject: [sv-bc] Confusion about case statement
	
	
	Please see the case:
	
	module test (output bit out1);
	
	parameter bit [1:0] p = 2'b1x;
	
	always@*
	    casex(2'b11)
	        {1'bx, p[0]} : out1 = 1'b1;
	        default : out1 = 1'b0;
	    endcase
	
	endmodule
	
	
	Here standard tools drives 'out1' with VSS. 
	
	
	However The Veirlog LRM IEEE1364-1995 says this (sec 9.5):
	
	"
	In a case expression comparison, the comparison only succeeds when each bit matches exactly with respect to the values
	0, 1, x, and z. As a consequence, care is needed in specifying the expressions in the case statement
	"
	
	"
	9.5.1 Case statement with donÕt-cares
	Two other types of case statements are provided to allow handling of donÕt-care conditions in the case comparisons.
	One of these treats high-impedance values (z) as donÕt-cares, and the other treats both high-impedance and unknown
	(x) values as donÕt-cares.
	These case statements can be used in the same way as the traditional case statement, but they begin with keywords
	casez and casex respectively.
	DonÕt-care values (z values for casez, z and x values for casex) in any bit of either the case expression or the case
	items shall be treated as donÕt-care conditions during the comparison, and that bit position shall not be considered.
	"
	
	Are we missing to interpret something here? 
	-- 
	Regards
	Surya

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