Re: [sv-bc] Query regarding clocking block signals

14.3 of Draft 6 is clear on this:

    It shall be illegal to write to a variable with a continuous
    assignment, a procedural continuous assignment, or a primitive
    when that variable is associated with an output clockvar.

The reason is essentially due to the error being reported by
the failing simulator - drives to variables are procedural
in nature and it is not legal to have a continuous and
procedural driver on a variable.

The 2009 draft has very substantial clarifications in this
area so it may be that some simulators are still following
other approaches.  However, under *any* approach I would
have expected an error on the example since if there is a
continuous driver it must be the only driver and clearly
the clocking block is also a driver of some form not matter
what a simulator does with it.

Gord.

Sarani Roy wrote:
> Hi,
> 
> According to LRM IEEE Std 1800-2005 Section 15.2 :
> 
> "All input or inout signals specified in the clocking block are sampled 
> when the
> corresponding clock event occurs. Likewise, *all output or inout signals 
> in the
> clocking block are driven when the corresponding clock event occurs*. 
> Bidirectional
> signals (inout) are sampled as well as driven. *An output signal cannot 
> be read*, and
> an input signal can-not be driven."
> 
> module top(input clk,input reg[3:0] in1, output reg[3:0] out1);
> 
> assign out1 = in1;
> 
> clocking clkB @ (posedge clk);
>  input in1;
>  output out1;
> endclocking
> 
> endmodule
> 
> Is the testcase given above valid?
> 
> Some standard simulators are passing this testcase while some others are
> giving the following error message:
> 
> "out1' is driven procedurally and continuously"
> 
> Thanks,
> Sarani
> 
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Gordon Vreugdenhil                                503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com


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