[sv-bc] Solve and before identifier

From: Surya Pratik Saha <spsaha_at_.....>
Date: Mon Jun 16 2008 - 10:47:34 PDT

Hi,
As per LRM,the syntax of solve and before is defined as:
constraint_block_item ::= solve identifier_list before identifier_list ;
| constraint_expression
identifier_list ::= identifier { , identifier }

Here you can see, LRM does not permit hierarchical reference in the identifier list of solve/before.But some simulators pass the following case:
module top;
class fp_operand;
  int operand;
endclass

class op_t;
  int operand;
endclass

class round_t;
  int operand;
endclass

class fp_transaction;

rand fp_operand a;
rand fp_operand b;
rand op_t    op;
rand round_t round;

constraint fair   { solve op before round, a.operand, b.operand;} // here the identifier list is consisting of hierarchical reference.

endclass
endmodule

Is there any plan to support it in SV in future? Is there already a mantis for that. Please let me know.

-- 
Regards
Surya

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