RE: [sv-bc] Upward referencing rules question

This is one of the most confusing parts of Verilog. I started using
Verilog in 1989 and I still don't have the rules straight in my mind.

Shalom 

> -----Original Message-----
> From: Bresticker, Shalom 
> Sent: Tuesday, February 12, 2008 11:43 AM
> To: sv-bc
> Subject: RE: [sv-bc] Upward referencing rules question
> 
> Actually, implementations differ on this case. Some print 5, 
> some give an error.
> 
> Shalom
>  
> 
> > No, searching has always been upwards in the hierarchy; 
> hence the name 
> > of the section describing this feature has always been 
> called "upwards 
> > name referencing"
> > 
> > The module a1 in the example is not on an upwards path to 
> the root of 
> > the hierarchy from the reference.
> > 
> > Dave
> > 
> > 
> > > -----Original Message-----
> > > From: Steven Sharp [mailto:sharp@cadence.com]
> > > Sent: Monday, February 11, 2008 4:22 PM
> > > To: Rich, Dave; shalom.bresticker@intel.com; sv-ec@eda.org; 
> > > danielm@aldec.com.pl
> > > Subject: RE: [sv-ec] Upward referencing rules question
> > > > > 
> > > >From: "danielm" <danielm@aldec.com.pl>
> > > 
> > > >So if this reference found as first wouldn't be a variable - then
> > search
> > > >should proceed? below example shold work and print '5' ? :
> > > 
> > > Yes.  It must work this way, because this is how Verilog 
> has always 
> > > worked for this case.
> 
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