Re: [sv-bc] Pre-Proposal to handle X-problems in RTL coding

From: Adam Krolnik <adam.krolnik_at_.....>
Date: Tue Nov 06 2007 - 08:40:06 PST
HI Cliff;

For proposal #3 and #4, (X-detection, X-assignment), I wonder why 
initialx, alway_ffx and always_latchx
are needed.

I'm sure initialx is added for consistency, but I don't see a general 
use for it.

I don't think always_ffx is useful. If you have an X on a clock, or a 
reset you will get warnings
for every block used. This compares with writing an assertion (that 
reports an error) when the clock
(or reset) is X. You have one strong error report vs. many weak warnings 
for the simulation user to review.
The enable likewise can be verified by a simple assertion.

I'd much rather have error reports vs. warnings. Too many people ignore 
warnings
because there is no way to remove their reporting if determined to be 
harmless. Most errors include
a way to suppress their report.  Compiler directives are excellent 
(though no standard ones exist) at
doing this.

Are there other ways of doing this work ? Mike does point out 
alternatives that are methodology based
rather than industry tool change based.




Clifford E. Cummings wrote:
> Hi, All -
>
> Could you peek at this pre-proposal to handle X-problems in RTL 
> coding? I have run this past engineers at ARM and they agree that this 
> would solve their RTL coding related X-problems.
>
> In short:
> (1) parallel_case equivalent using a new keyword: unique0
> (2) X-trapping using new keywords: initialx, alwaysx, always_combx, 
> always_latchx, always_ffx
>
> Addresses Mantis items: 99, 2115, 2129, 2131, 2132
>
> Regards - Cliff
>
> ----------------------------------------------------
> Cliff Cummings - Sunburst Design, Inc.
> 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
> Phone: 503-641-8446 / FAX: 503-641-8486
> cliffc@sunburst-design.com / www.sunburst-design.com
> Expert Verilog, SystemVerilog, Synthesis and Verification Training
>

-- 
    Soli Deo Gloria
    Adam Krolnik
    Director of Design Verification
    VeriSilicon Inc.
    Plano TX. 75074
    Co-author "Assertion-Based Design", "Creating Assertion-Based IP"


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Received on Tue Nov 6 08:43:07 2007

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