[sv-bc] Pre-Proposal to handle X-problems in RTL coding

Hi, All -

Could you peek at this pre-proposal to handle X-problems in RTL 
coding? I have run this past engineers at ARM and they agree that 
this would solve their RTL coding related X-problems.

In short:
(1) parallel_case equivalent using a new keyword: unique0
(2) X-trapping using new keywords: initialx, alwaysx, always_combx, 
always_latchx, always_ffx

Addresses Mantis items: 99, 2115, 2129, 2131, 2132

Regards - Cliff

----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com
Expert Verilog, SystemVerilog, Synthesis and Verification Training

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