RE: [sv-ac] Re: [sv-bc] Re: if-else

Steven,

You are correct regarding 0 sized bit vector declarations. However, I do
believe you can use dynamically sized types in integral expressions. For
example:

  logic [4:0] b [];	// dynamic array

  initial if( b[0] ) ...	// empty integral type

I believe in such cases, Verilog treats the empty reference as 'X.

    Arturo

-----Original Message-----
From: Steven Sharp [mailto:sharp@cadence.com] 
Sent: Thursday, November 01, 2007 12:06 PM
To: Eduard.Cerny@synopsys.COM; john.havlicek@freescale.com;
Arturo.Salz@synopsys.COM
Cc: sharp@cadence.com; sv-ac@eda.org; sv-bc@eda.org
Subject: RE: [sv-ac] Re: [sv-bc] Re: if-else


>From: "Arturo Salz" <Arturo.Salz@synopsys.com>

>I believe it can happen with parameters (example below) and dynamically
>sized types.
>
>   module M #(size = 8) (input logic clk);
>     logic [size-1:0] v;
>
>     always @(posedge clk)
>        if( v ) ...
>   endmodule
>
>   M #(1) M1 (phi1);


No, this creates a declaration "logic [0:0] v;", which is a 1-bit
vector containing only v[0].  And if you try overriding size to 0,
you will get "logic [-1:0] v;", which is a 2-bit vector.  It is not
possible to declare a 0-bit vector in Verilog.  This is not an
accident.

I don't think any dynamically sized types can be used in integral
expressions, so this issue shouldn't come up there either.

Steven Sharp
sharp@cadence.com


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