>From: "Arturo Salz" <Arturo.Salz@synopsys.com> >I believe it can happen with parameters (example below) and dynamically >sized types. > > module M #(size = 8) (input logic clk); > logic [size-1:0] v; > > always @(posedge clk) > if( v ) ... > endmodule > > M #(1) M1 (phi1); No, this creates a declaration "logic [0:0] v;", which is a 1-bit vector containing only v[0]. And if you try overriding size to 0, you will get "logic [-1:0] v;", which is a 2-bit vector. It is not possible to declare a 0-bit vector in Verilog. This is not an accident. I don't think any dynamically sized types can be used in integral expressions, so this issue shouldn't come up there either. Steven Sharp sharp@cadence.com -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Thu Nov 1 12:06:36 2007
This archive was generated by hypermail 2.1.8 : Thu Nov 01 2007 - 12:07:02 PDT