[sv-bc] SVDB 1619 Examples

Hi, All -

Attached is a tar-file with three 2-flop pipeline models.

pipe1.v has reset going to the second flop but not the first. Synthesizes fine.
pipe2.v has different resets going to the different flops. The first 
flop reset is internally tied through a continuous assignment to a 
variable initialized in the declaration (the closest I can get to 
1619 with current coding styles) while the second reset comes in 
through a port. Try synthesizing that model and tell me what you get 
(I used DC and warnings about ignored initializations and both flops 
disappear).
pipe3.v is the 1619 proposed equivalent to pipe2.v

This is why I am concerned.

Regards - Cliff

At 12:44 PM 10/14/2007, Jonathan Bromley wrote:
>Re. 1619 (defaults on module inputs):  Cliff said
>
> > If Synopsys supports this in synthesis, then
> > other tools could be shamed into supporting
> > this feature.
>
>I fear the boot is somewhat on the other foot.  For
>some time Synopsys DC was the only synth tool I know
>about that didn't correctly support VHDL's default
>inputs on modules (it accepted the syntax, but
>defaulted the inputs to zero regardless of the
>specified value); it's fine nowadays, though.
>All the FPGA-oriented tools have supported VHDL
>default inputs correctly since forever.  This
>is old, well-cooked technology.
>
> > There are other synthesis tools, like Synplicity,
> > that ignore initial blocks and hence initial
> > assignments
>
>Surely the default is a constant_expression, and so
>no "initial" block is implied or needed?
>--
>Jonathan Bromley, Consultant
>
>DOULOS - Developing Design Know-how
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>
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Cliff Cummings - Sunburst Design, Inc.
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