Re. 1619 (defaults on module inputs): Cliff said > If Synopsys supports this in synthesis, then > other tools could be shamed into supporting > this feature. I fear the boot is somewhat on the other foot. For some time Synopsys DC was the only synth tool I know about that didn't correctly support VHDL's default inputs on modules (it accepted the syntax, but defaulted the inputs to zero regardless of the specified value); it's fine nowadays, though. All the FPGA-oriented tools have supported VHDL default inputs correctly since forever. This is old, well-cooked technology. > There are other synthesis tools, like Synplicity, > that ignore initial blocks and hence initial > assignments Surely the default is a constant_expression, and so no "initial" block is implied or needed? -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 Email: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Sun Oct 14 12:44:28 2007
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