>From: "Brad Pierce" <Brad.Pierce@synopsys.com> > >According to > > http://www.eda-stds.org/svdb/view.php?id=1058 > http://www.eda-stds.org/svdb/view.php?id=1224 > >the LRM currently allows the parameter values in module instantiations >to be hierarchical references, for example > > mod#(.P(mod_inst2.P) mod_inst1(...); > mod#(.P(mod_inst1.P) mod_inst2(...); > >Are real users doing this kind of tricky stuff? How badly would it >break backward compatibility to disallow this starting in 2008? It must happen occasionally, since NC-Verilog allowed it in order to match Verilog-XL. Perhaps we could disallow it in the LRM, and tools could still allow it with warnings, to let legacy code continue to work. BTW, there is no reason to disallow it for delays on UDPs. But those look syntactically identical to parameter overrides by position on module instantiations. They cannot be distinguished until elaboration. Steven Sharp sharp@cadence.com -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Fri Sep 21 18:06:26 2007
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