Re: [sv-bc] XMRs in parameter value overrides of module instantiations

Is your example legal?  My concern is that, when mod_inst1 is
instantiated, mod_inst2 has not been defined/declared.

In parameter declarations, one can reference other
*previously-declared* parameter values:
     parameter p1 = 0;
     parameter p2 = p1 + 5;
but you can't swap the order of the declarations (nor make the
defaults circular).

The Verilog-AMS committee has had some thoughts about having
a "process constants" module that would contain, eg, TOX for
both PMOS and NMOS, and the MOS modules would then use a
hierarchical reference to obtain TOX, which would then allow it
to be modified in one place to model process variation.

-Geoffrey




Brad Pierce wrote:
> According to
> 
>     http://www.eda-stds.org/svdb/view.php?id=1058
>     http://www.eda-stds.org/svdb/view.php?id=1224
> 
> the LRM currently allows the parameter values in module instantiations
> to be hierarchical references, for example
> 
>     mod#(.P(mod_inst2.P) mod_inst1(...);
>     mod#(.P(mod_inst1.P) mod_inst2(...);
> 
> Are real users doing this kind of tricky stuff?  How badly would it
> break backward compatibility to disallow this starting in 2008?
> 
> -- Brad
> 

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