RE: [sv-bc] SV Methods and Mantis 902

From: Rich, Dave <Dave_Rich_at_.....>
Date: Tue Sep 18 2007 - 07:08:17 PDT
Tom,
 
What you say is true for some RTL design styles that can be completely describes in terms a thread of procedural statements, and you are not talking about class methods. If your methods need to spawn other threads either by fork/join or fork/join_none, that is currently not synthesizable with the currently available synthesis tools.
 
If you are talking about class methods, that is not currently synthesizable either because the construction of a class is dynamically allocated object. However, a few people have suggested that
 
const classname classvar = new();
 
could be treated as a static class. I'm sure there would be other restrictions on the use of classvar as well.
 
Dave

 
________________________________

From: owner-sv-bc@server.eda.org on behalf of Alsop, Thomas R
Sent: Mon 9/17/2007 11:10 AM
To: sv-bc@server.eda.org
Subject: [sv-bc] SV Methods and Mantis 902



I want to follow up with today's discussion on Mantis 902.   My perspective on this issue from a design standpoint is that this is a very important feature.  However, I am a little confused on the need given what is already defined within SV methods.  

 

First let me explain what I want as a designer.  I want to be able to code up a block of logic which has a well defined set of interface and protocols and abstract that protocol into methods (functions and tasks).  These methods in essence contain all the logic necessary for anyone else who wants to communicate with me to simply call my methods.  Instead of those callers having to understand all the details of every wire they only need to understand the higher level details of the method they are using and how to connect into it.   

 

This method is synthesizable in the caller's blocks as long as they are declared as automatic.

 

My question then is how 902 improves on SV methods? Why do we need module instantiation if we already have methods?  

 

Most of what I understand from methods comes directly from Stu's "SystemVerilog for Design", so that is what I am basing on my understanding of methods.

 

Thanks, -Tom


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Received on Tue Sep 18 07:08:46 2007

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