[sv-bc] SV Methods and Mantis 902

I want to follow up with today's discussion on Mantis 902.   My
perspective on this issue from a design standpoint is that this is a
very important feature.  However, I am a little confused on the need
given what is already defined within SV methods.  

 

First let me explain what I want as a designer.  I want to be able to
code up a block of logic which has a well defined set of interface and
protocols and abstract that protocol into methods (functions and tasks).
These methods in essence contain all the logic necessary for anyone else
who wants to communicate with me to simply call my methods.  Instead of
those callers having to understand all the details of every wire they
only need to understand the higher level details of the method they are
using and how to connect into it.   

 

This method is synthesizable in the caller's blocks as long as they are
declared as automatic.

 

My question then is how 902 improves on SV methods? Why do we need
module instantiation if we already have methods?  

 

Most of what I understand from methods comes directly from Stu's
"SystemVerilog for Design", so that is what I am basing on my
understanding of methods.

 

Thanks, -Tom


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