"Real" experts will no doubt comment in due course, but as a user I think I know the answer and it would be interesting to see if implementers agree: > module top( output out1,input in1); > endmodule > > module mid(output X,input Y); > endmodule > > module root(output a, input b); > top I(a,b); > endmodule > > bind top mid mid_inst(out1,in1); > bind mid top top_inst(X,Y); The mental model I use for 'bind' is that it inserts a module instance at the very end of the target module. So I can re-write your code: module top( output out1,input in1); mid mid_inst(out1,in1); // inserted by bind endmodule module mid(output X,input Y); top top_inst(X,Y); // inserted by bind endmodule module root(output a, input b); top I(a,b); endmodule It's now clear that the module instance tree has unbounded mutual recursion, so the model cannot be elaborated. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 Email: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Mon Sep 10 01:00:58 2007
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